1. Field
Example embodiments relate to a nonvolatile semiconductor memory device and a method of making the same. Other example embodiments relate to a nonvolatile semiconductor memory device wherein characteristics of a memory cell and a peripheral cell may be optimized or improved and a method of making the same.
2. Description of the Related Art
Nonvolatile semiconductor memory devices may be capable of storing data even after an external power supply is removed. To achieve this function, nonvolatile devices may be supplied with a floating layer upon which charges may be stored or removed depending on a program or erase status of the device. Two types of such floating layer devices may include a floating gate type device and a floating trap type device.
A floating gate type device may include a conductive gate layer that floats due to its isolation by a surrounding insulating layer. The floating gate may be isolated from a substrate channel below and from a control gate above. The floating gate type device may be respectively programmed and erased by storing and removing charges as free carriers on the conductive floating gate. A floating trap type device may include a non-conductive layer that may be floating between a substrate channel and a control gate. The floating trap type device may be programmed and erased by storing and removing charges in traps in the non-conductive floating layer.
A known type of floating trap type device may be a silicon-oxide-nitride-oxide-semiconductor (SONOS) device. A SONOS device may include a tunneling insulating layer on a substrate, a charge storage layer on the tunneling layer, a blocking insulating layer on the charge storage layer and a gate electrode on the blocking layer. The substrate may include a P-type silicon substrate having N-type impurity layers formed on either side of the gate electrode as a source and drain. Thermal oxide may be used to form the tunneling layer and silicon nitride may be used as the charge storage layer. During operation, charges may be moved to and from the charge storage layer from and to the substrate in order to program and erase the memory cell.
To address certain shortcomings of SONOS technology, a floating trap type memory device including a metal (e.g. tantalum) layer, a high-k dielectric (e.g. aluminum oxide) layer, and a nitride-oxide-semiconductor layered structure (TANOS) has been introduced. In a TANOS device, a gate may be made of a metal, for example tantalum, and a blocking layer may be made of a high-k dielectric material, for example, aluminum oxide. The use of a high-k dielectric material as a blocking layer may be a significant feature of the TANOS architecture. Additional features of a TANOS device may include a high work function layer and a barrier metal layer as part of the gate electrode structure. TANOS technology may be disclosed in U.S. Pat. No. 6,858,906, and various additional TANOS related technologies have been proposed, for example in U.S. Patent Application Publications 2004/0169238 and 2006/0180851, the entire disclosures of all of which are hereby incorporated by reference. Efforts towards improving the performance and function of the TANOS technology and optimizing or improving the architecture of the TANOS device, including its gate structure, are continuing.
Along with the floating trap type memory cells, e.g., a TANOS cell, a nonvolatile memory device may also be formed having peripheral regions. The peripheral regions may include various devices, e.g., MOS transistors, which may be used for programming, erasing and otherwise controlling the memory cells. Typically, the MOS transistors of the peripheral region have gate electrodes formed of a silicon material, e.g., doped poly-silicon.
As the demand for capacity of such nonvolatile memories increases, a line width of patterns used to form the transistors may be decreasing. The reduction in line widths correlates to an increase in the resistance of the conductive patterns, e.g., the gate electrodes of the peripheral transistors, and causes a corresponding increase in the resistance-capacitance (RC) delay. For example, if a line width of a transistor's gate electrode may be decreased and its resistance increased, an RC delay associated with the transistor may be increased, thus causing an increased operating time of the transistor and its corresponding circuit.
One proposed method to address the increased resistance is to include a material having a decreased resistivity as part of the peripheral gate electrode, e.g., tungsten (W). Compared to doped poly-silicon which has a resistivity of about 10−5 Ω-m, tungsten has a resistivity of about 5.5×10−8 Ω-m which may be several orders of magnitude less than that of doped poly-silicon. Therefore, the line widths of the peripheral devices may be decreased without an increase in RC delay. Moreover, a processing convenience is provided in that a relatively high conductivity metal, e.g., tungsten or tantalum, used in a TANOS cell may also be used in forming the peripheral cell.
However, in a peripheral MOS transistor, tungsten and other relatively low resistivity metals may react and diffuse with underlying layers, e.g., poly-silicon, and may cause deterioration of the transistor's reliability. To address this concern, a barrier metal layer may be placed between the tungsten layer and underlying poly-silicon layer. Generally, a metal nitride may be used as the barrier metal to prevent or retard reaction and diffusion of tungsten. Using the barrier metal layer may provide another processing convenience because a same barrier metal used in the TANOS process may be used in forming the peripheral transistors. However, the use of the metal nitride layer between the tungsten and poly-silicon layers may cause an increase in the interface resistance between the poly-silicon and the tungsten. Because the interface resistance may be increased, a program voltage pulse may not be sufficient for programming the memory cell and the RC delay may again be increased.
In a conventional TANOS memory circuit having a peripheral region, a relatively low resistivity metal layer used in the TANOS memory cell may also be used as an overlying layer in the peripheral transistor. For example, in the peripheral region, the relatively low resistivity layer may overlay a poly-silicon gate layer so as to lower the gate resistance. However, use of the relatively low resistivity metal layer may require that a barrier metal layer be used to avoid reaction and/or diffusion. Unfortunately, the use of the barrier metal layer may cause an increase in the interface resistance, thereby causing a voltage drop and potential failure to generate an appropriate level of program voltage pulse.